Many logic circuits employ current-injection logic (I.sup.2 L) design which is noted for its simplicity and high density (large number of transistors per unit area). In speakerphone applications, for example, I.sup.2 L logic is useful as a serial communication interface port because of its high density and compatibility with the bipolar processes used in other components of the system. A common problem with I.sup.2 L technology is the limited fan-out capability of the logic circuits which is typically constrained to driving three or four other gates connected to the output thereof. Driving an excessive number of output logic gates increases the rise and fall times of the logic signals. One solution to the limited fan-out problem of I.sup.2 L circuits is the use of a distribution tree wherein the output signal of one gate drives the inputs of say three other gates while the outputs of the latter three gates each drive three additional gates. Thus, it is possible for one logic signal to multiply through a four level distribution tree and drive eighty-one other logic circuits. However, the inherent propagation delay through the distribution tree also introduces a timing skew between the input signal and the plurality of output signals which may be unacceptable in many applications.
Hence, what is needed is an improved I.sup.2 L synchronous driver with improved fan-out capability without inducing appreciable timing skew between the input signal and output signals thereof.